1. Field of the Invention
The present invention relates to a method of manufacturing a non-volatile semiconductor memory device. More particularly, the present invention relates to a method of manufacturing a non-volatile semiconductor memory device that includes a silicon oxide-nitride-oxide semiconductor (SONOS) or a metal oxide-nitride-oxide semiconductor (MONOS) memory cell having a split structure.
2. Description of the Related Art
Generally, semiconductor memory devices can be divided into volatile semiconductor memory devices, such dynamic random access memory (DRAM) devices or static random access memory (SRAM) devices, and non-volatile semiconductor memory devices, such as electrically erasable programmable read only memory (EEPROM) devices. Data stored in the volatile memory devices is lost once power to the devices is interrupted, whereas the non-volatile memory devices can maintain stored data for a predetermined period even after power to the devices is interrupted.
Non-volatile memory devices rely on Fowler-Nordheim (F-N) tunneling or the hot-carrier injection of thermal electrons to control the input or output of data. More specifically, the programming of a non-volatile memory device is initiated by impressing positive voltage across a control gate of the device. The positive voltage is coupled to a floating gate to thereby cause electrons to be captured by the floating gate. On their way to the floating gate, the electrons pass through a tunnel oxide layer on a substrate by means of F-N tunneling or hot-carrier injection. On the other hand, the erasing of the non-volatile memory device entails impressing a negative voltage across the control gate so that electrons in the floating gate move toward the substrate. The response speed of the non-volatile memory device corresponds to the coupling ratio. Here, the term “coupling ratio” refers to the ratio of the voltage applied to the control gate and the voltage coupled to the floating gate during the programming operation.
Non-volatile semiconductor devices have been recently employing a floating gate structure and a metal insulator semiconductor (MIS) structure having two or three dielectric layers. An EEPROM tunnel oxide (ETOX) structure is a well-known floating gate structure in which the programming and erasing operations are carried out using a potential well. Meanwhile, MONOS and SONOS structures are widely known MIS structures in which the programming and erasing operations are performed using a trap existing in a dielectric bulk, i.e., at the boundary between two dielectric layers or at the boundary between a dielectric layer and a semiconductor substrate. Korean Laid-Open Patent Publication No. 2003-57897 discloses a non-volatile semiconductor memory device including an SONOS memory cell.
FIG. 1 illustrates such a conventional SONOS memory cell of a non-volatile semiconductor memory device.
Referring to FIG. 1, a gate structure of the SONOS memory cell includes a dielectric layer 20 formed on a semiconductor substrate 10, and a polysilicon layer 22 formed on the dielectric layer 20. The polysilicon layer 22 constitutes a control gate of the non-volatile semiconductor memory device. Source/drain regions 12a and 12b are formed at portions of the substrate 10 adjacent to the gate structure.
The dielectric layer 20 has an oxide-nitride-oxide (ONO) structure in which a first oxide film 14, a nitride film 16 and a second oxide film 18 are disposed one atop the other on the substrate 10. The first oxide film 14 serves as a tunneling oxide film and the second oxide film 18 functions as a blocking oxide film.
Although the above-described non-volatile semiconductor memory device including the SONOS memory cell is relatively small, the non-volatile semiconductor memory device may have relative high threshold voltage (Vth) and programming current because the dielectric layer of the ONO structure is situated on a channel region of the substrate where the gate structure is located. Additionally, an incomplete erasing of data may occur in the SONOS memory cell.
Japanese Laid-Open Patent Publication No. 2000-201115 discloses a non-volatile semiconductor memory device having an improved SONOS memory cell that aims to overcome such problems. And, U.S. Pat. No. 6,011,725 discloses a non-volatile semiconductor memory device having a split-structured SONOS memory cell in which a dielectric layer is formed beneath a control gate.
FIGS. 2A to 2F illustrate a conventional method of manufacturing a non-volatile semiconductor memory device having a split-structured SONOS memory cell.
Referring to FIGS. 2A and 2B, a dielectric layer pattern 60 having an ONO structure is formed on a substrate 50. The dielectric layer pattern 60 includes a first oxide film 54, a nitride film 56 and a second oxide film 58 successively formed on the substrate 50. The dielectric layer pattern 60 traps electrons in the memory cell of the non-volatile semiconductor memory device.
Next, a polysilicon layer 70 is formed on the dielectric layer pattern 60 and on the substrate 50.
Referring to FIGS. 2C and 2D, after an etching mask (not shown) is formed on the polysilicon layer 70, the polysilicon layer 70 is patterned using the etching mask to thereby form a polysilicon layer pattern 70a. The polysilicon layer pattern 70a has a split structure, and exposes a predetermined portion of the dielectric layer pattern 60. In this case, the polysilicon layer pattern 70a serves as a control gate of the split-structured memory cell.
The etching mask is removed. Preliminary source/drain regions 52a and 52b are then formed on the substrate 50 by implanting impurities into the substrate 50 using the polysilicon layer pattern 70a as a mask. At this time, the preliminary source region 52a may be rather wide because the ion implantation process for forming the source/drain regions 52a and 52b must be carried out with a relatively high energy considering that the impurities must penetrate the dielectric layer pattern 60.
Referring to FIGS. 2E and 2F, a nitride layer 72 is formed on the substrate 50. Then, the nitride layer is etched using an etch back process to thereby form a spacer 72a on the sidewall of the polysilicon layer pattern 70a. At this time, the dielectric layer pattern 60 is to be separated into two parts 60a by the etch back process. Thus, a portion of the substrate 50 including the drain region 52b may be over-etched during the etch back process, thereby creating a defect such as a recess R on the substrate 50.
Finally, impurities are implanted into the substrate 50 using the polysilicon layer pattern 70a and spacer 72a as a mask to form lightly doped structures 54a and 54b in the preliminary source/drain regions 52a and 52b of the substrate 50.
However, in the non-volatile semiconductor memory device having the above-described SONOS memory cell, the width of the channel region of the SONOS memory cell is relatively small and the programming efficiency of the non-volatile semiconductor memory device is mediocre because the source region 52a has a relatively large width and inclined profile. Additionally, leakage current may occur at the drain region due to the defect, such as the recess R, created as the result of the over-etching of the substrate during the etch back process used to split the gate structure. Accordingly, a non-volatile semiconductor memory device manufactured according to the above-described conventional method is not so reliable.